Incoming Design Verification Engineering Intern
- Selected for an 8-month co-op on the design verification team for AMD's chiplet interconnect hardware: SystemVerilog/UVM test development, register testing, and regression infrastructure and automation
Computer engineering · design verification — Vancouver, BC
Anant
Khanna
I work where hardware meets software — SystemVerilog and testbenches on FPGAs, GPU inference pipelines, and the systems around them. Computer Engineering @ UBC, joining AMD's chiplet interconnect design verification team in 2027.
01 / About
Every layer of the machine
I'm a Computer Engineering student at the University of British Columbia (Co-op, Dean's List 2025) who likes working at every layer of the machine — SystemVerilog on an FPGA one day, a transformer embedding pipeline the next.
In May 2027 I'm joining AMD in Vancouver as a Design Verification Engineering Intern on the team that builds AMD's chiplet interconnect hardware — an 8-month co-op writing SystemVerilog/UVM tests and regression infrastructure. The hardware work that got me there: a pipelined neural-network accelerator on a DE1-SoC, verified against a reference model (and debugged by waveform when the pipeline wouldn't drain), and a SystemVerilog CPU with self-checking testbenches in QuestaSim.
On the software side I lead the ML team at UBC UAS, where our vision pipeline detects targets in real time from a drone moving at 50+ km/h on a Jetson Orin Nano; I've benchmarked inference across an RTX 3080 and an MI300X; and over summer 2026 I was a founding software engineer at Agriprix, a B2B agricultural marketplace. I'm also the lead developer of UBC Finds, a live lost-and-found map for campus.
Off the clock I build games — two of them placed top-5 in back-to-back game jams — and I've taught programming to 120+ kids as an instructor at Code Ninjas.
Currently — 3rd-year CE @ UBC · ML Lead @ UBC UAS · Incoming DV Intern @ AMD (May 2027)
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inferences/sec, FPGA neural-net accelerator
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speedup over ARM-only execution
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fps, MIGraphX FP16 on an AMD MI300X
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top-5 game jam finishes
02 / Experience
Where I've worked
Founding Software Engineer
- Rebuilt the hybrid intent router (deterministic rules + LLM classification) for an agent platform spanning 70+ tools; added per-call token/latency observability with automatic failover across 5 model providers
- Implemented Stripe authorize-and-capture checkout with deterministic idempotency keys, an integer-cent commission pricing engine, and per-farm fulfillment state machines for multi-supplier orders
- Led a platform security audit surfacing 67 vulnerabilities (5 critical) — patched mass-assignment/IDOR serializers, eliminated overselling races via row-level locking, shipped a 15-case Playwright E2E suite covering the supplier-to-buyer order journey
- Built a WhatsApp AI assistant on the WhatsApp Business Cloud API, routing inbound webhooks into the agent layer so buyers and suppliers can transact directly over chat
Machine Learning Team Lead
- Real-time autonomous object detection (YOLOv11) on an NVIDIA Jetson Orin Nano moving at 50+ km/h — 95% detection accuracy, +22% mAP
- Metric-learning re-identification with Vision Transformer embeddings, invariant to lighting and orientation
- TensorRT FP16 quantization: 50% less memory bandwidth within 0.5% of baseline precision
Lead Developer
- Built a campus utility finder map on React/Next.js and Supabase, architecting event-driven state synchronization over Supabase realtime channels that eliminates race conditions through atomic writes
- Optimized report aggregation and live map rendering for low-latency updates as new utility reports stream in
Programming Instructor
- Designed and delivered 15+ project-based C#/JavaScript curricula for 120+ students
03 / Projects
Things I've built
FIG. H
FPGA Neural-Net Inference Accelerator
A single-layer neural network (MAC unit) on a DE1-SoC in SystemVerilog, pipelined into load / multiply / accumulate stages to shorten the critical path, with a 24-bit accumulator sized from bit-growth analysis. Verified against a reference model with a self-checking testbench covering the corner cases; a pipeline-drain bug (the final result never flushing through) was found by waveform analysis of valid-in/valid-out timing and fixed with a drain state. A memory-mapped C++ driver on the ARM HPS under embedded Linux reaches 3,000 inferences/sec — a 300% speedup over ARM-only execution.
FIG. I
Digital Systems Design
A CPU datapath and control (ALU, register file, control FSM) and a debounced keyboard interface with a two-flop synchronizer, in SystemVerilog on a DE10-Lite. Self-checking, vector-driven testbenches in QuestaSim: golden vectors loaded from file, stimulus driven and checked on opposite clock edges, four-state comparison, pass/fail reporting.
FIG. J
GitHub ↗
GPU Inference Benchmark
Cross-stack inference benchmark isolating compilation gains from precision gains with a three-rung
ladder (PyTorch to TensorRT FP32 to TensorRT FP16) on an RTX 3080 — 50 warmup runs discarded,
torch.cuda.synchronize() around every timing, median/p95 against a
measured ±0.5 ms noise floor. Then ported to AMD's MI300X via ROCm/MIGraphX, where unoptimized
PyTorch FP32 (1,143 fps) already beats the fully-optimized TensorRT FP16 engine on the 3080
(1,008 fps) on raw hardware scale, and MIGraphX FP16 scales from batch 1 to 8 to 7,277 fps with
near-zero added latency.
Wealth Council
Agentic investment platform: a multi-agent orchestration layer (Fetch.ai uAgents) computes portfolio risk while FinBERT runs sentiment analysis on live financial news, and Gemini synthesizes the final report — streamed to React in real time over SSE.
FIG. L
GitHub ↗
GuardCam
Edge-to-cloud driver monitoring that catches micro-sleeps: a custom TCP WebSocket bridge streams video with minimal latency to a headless GPU server, where a 468-point face mesh computes Eye Aspect Ratio and fires sub-second haptic alerts.
FIG. M
GitHub ↗
AetherShell
An AI-powered PowerShell assistant: natural language in, safe shell commands out. Open source under MIT.
FIG. N
Campus Noise Map
IoT network of Raspberry Pi Zero 2 W nodes tracking real-time noise across UBC, with TensorFlow's YAMNet classifying the noise source — so students can find a quiet place to study.
FIG. O
2× top-5, back-to-back jams
Cell Fusion & Blink
Two complete games shipped under game-jam time limits: Cell Fusion (puzzle-strategy, 5th of 81) and Blink (narrative platformer with a time-blink mechanic, 4th of 86).
More on GitHub ↗
04 / Skills
Toolbox
Hardware / RTL
SystemVerilog · Verilog · Intel Quartus · QuestaSim · Platform Designer · Digital Design · Computer Architecture · ARM SoCs
Verification
Self-checking testbenches · Reference models · Simulation & waveform debugging · Corner-case tests · UVM fundamentals
Languages
Python · C · C++ · C# · Java · JavaScript · TypeScript · SQL · RISC-V & ARM Assembly
Frameworks & GPU
PyTorch · TensorFlow · CUDA / TensorRT · ROCm / MIGraphX · YOLO / Ultralytics · Django / DRF · FastAPI · React · Next.js
Tools & Cloud
Google Cloud Platform · Docker · PostgreSQL · MySQL · Supabase · Stripe · Playwright · Git · Linux
05 / Contact
Get in touch
Whether it's an opportunity, a collaboration, or you just want to talk FPGAs and neural nets —
my inbox is always open. Or skip the formalities — open the terminal (bottom right, or below)
and type sudo hire-anant.
GitHub LinkedIn itch.io Résumé